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第一作者：Jipeng Wang

通讯作者：C. Wang*

合写作者：Jihui Song, B. Liu, Z. Shen, Y. Jiang, F An, J. Tang

发表刊物：2023 IEEE International Industrial Electronics Conference (IECON 2023)

收录刊物：EI

学科门类：工学

一级学科：电子科学与技术

文献类型：C

DOI码：10.1109/IECON51785.2023.10311903

发表时间：2023-07-17

摘要：This paper proposes a Histogram of Oriented Gradients-Support Vector Machine (HOG-SVM) based pedestrian detector with an end-to-end fully-pipelined architecture to achieve a high frame rate by improving the throughput, and reduce the power consumption by minimizing the data movement. To further improve the energy efficiency under the high frame rate, a bit-width pruning method is used to remove the gray-scale converter’s redundant data bit width, and a block-score normalization is employed to significantly reduce the normalizer’s required divisions. The reduced computation amount also saves the hardware overhead while maintaining the same calculation accuracy. Besides, a modeling and analysis method of the SVM-classifier-Multiply-ACcumulate (MAC) array is proposed to further improve the energy efficiency and save the logic resources, by optimizing the array size with a hardware utilization of 98.4% while maintaining the same throughput. The FPGA implementation results of 640×480 video show a high frame rate of up to 439 fps @143 MHz and a high energy efficiency of 0.76 nJ/pixel with 46.7% fewer LUTs, 22.4% fewer registers, 88.3% fewer DSPs, compared to the state-of-the-art design. The ASIC implementation in 55 nm also confirms a high energy efficiency of 0.35 nJ/pixels at 613 fps and 200 MHz as well as a hardware overhead of 177 k gates and 108 Kbits SRAM.

发布期刊链接：https://ieeexplore.ieee.org/document/10311903