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第一作者：Z. Shen

通讯作者：C. Wang*

合写作者：, L. Huang, Y. Zhao, K. Yang, J. Wang, B. Liu, B. Dong, Z. Wei, Y. Zheng, and

发表刊物：2024 International Conference on IC Design and Technology (ICICDT 2024)

收录刊物：EI

学科门类：工学

一级学科：电子科学与技术

文献类型：C

发表时间：2024-08-25

摘要：In this paper, an energy-efficient low-voltage 7T SRAM-based charge recovery logic NMC macro is proposed. Firstly, a weight-stationary NMC macro architecture in dual clock and voltage domains is proposed to save memory energy consumption at near-threshold regime, without sacrificing computing throughput. Secondly, the charge recovery logic at subthreshold regime is also employed to reduce NMC logic energy consumption, while maintaining the computing speed. Simulation results show that the energy efficiency of the proposed 4Kb 7T-SRAM based CRL NMC macro design is around 3.71 TOPS/W, i.e., 6.49× improvement against the baseline design, when accelerating convolutional operations by 1.8 GOPS at 100 MHz with SRAM operating under 0.6 V and CRL computing under 0.4 V.