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A 28-nm 0.23fJ/OP, 0.41 LSB Average Absolute Error Reconfigurable Merged-in-ADC Computing Circuit with Novel Parasitics-induced Error Elimination
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第一作者：W. Zhu, Y. Zhao
通讯作者：C. Wang*
合写作者：L. Huang, Z. Zhang, Y. Yang, Y. Zheng
发表刊物：2025 IEEE Interregional NEWCAS Conference (NEWCAS 2025)
收录刊物：EI
学科门类：工学
一级学科：电子科学与技术
文献类型：C
摘要：High-energy-efficiency and high-linearity analog and mixed-signal domain computing is one of the cutting-edge research trends in intelligent edge sensors. This paper proposes a merged-in-ADC reconfigurable three-mode switched-capacitor computing circuit to achieve a good linearity by a novel top/bottom-plate alternating based input and charge sharing method. Multiplication is implemented by a new 4-phase switching scheme to eliminate the parasitic capacitance induced additive error, while also effectively reducing latency and power consumption. The prototype chip at 28-nm CMOS demonstrates a high energy efficiency of 0.23 fJ/OP with an accuracy of 0.41 LSB average absolute error, outperforming the state-of-the-art designs.