Indexed by: Journal paper

First Author: Xingsheng Wang

Correspondence Author: Xingsheng Wang

Co-author: X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif,A. Asenov

Journal: IEEE Design & Test

Included Journals: SCI、EI

Affiliation of Author(s): University of Glasgow

Document Type: J

Volume: 30

Issue: 6

Page Number: 18-28

Key Words: co-design , finFET , half select disturb , reliability , SRAM , stability , static noise margin , variability

Date of Publication: 2011-11-01

Abstract: This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence of statistical variability and reliability impact. As statistical variability sources random discrete dopants, gate-edge roughness, fi-edge roughness, metal-gate granularity and random interface trapped charges in N/PBTI are considered.

Links to published journals: https://ieeexplore.ieee.org/document/6525375/?arnumber=6525375