A 28-nm 0.23fJ/OP, 0.41 LSB Average Absolute Error Reconfigurable Merged-in-ADC Computing Circuit with Novel Parasitics-induced Error Elimination

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First Author:W. Zhu, Y. Zhao

Correspondence Author:C. Wang*

Co-author:L. Huang, Z. Zhang, Y. Yang, Y. Zheng

Journal:2025 IEEE Interregional NEWCAS Conference (NEWCAS 2025)

Included Journals:EI

Discipline:Engineering

First-Level Discipline:Electronic Science And Technology

Document Type:C

Abstract:High-energy-efficiency and high-linearity analog and mixed-signal domain computing is one of the cutting-edge research trends in intelligent edge sensors. This paper proposes a merged-in-ADC reconfigurable three-mode switched-capacitor computing circuit to achieve a good linearity by a novel top/bottom-plate alternating based input and charge sharing method. Multiplication is implemented by a new 4-phase switching scheme to eliminate the parasitic capacitance induced additive error, while also effectively reducing latency and power consumption. The prototype chip at 28-nm CMOS demonstrates a high energy efficiency of 0.23 fJ/OP with an accuracy of 0.41 LSB average absolute error, outperforming the state-of-the-art designs.