BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems

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Indexed by:Journal paper

Co-author:C. Wang, J. Zhou, R. Weerasekera, B. Zhao, X. Liu, P. Royannez,M. Je

Journal:IEEE Trans. on Circuits and Systems-I Regular Papers (TCAS-I) 2015

Included Journals:SCI

Volume:62

Issue:1

Page Number:139-148

DOI number:10.1109/TCSI.2014.2354752

Date of Publication:2014-10-08

Abstract:This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan switch network (SSN) architecture is proposed to perform pre-bond TSV scan testing in test mode, and operate as functional circuit in functional mode, respectively. In the SSN, novel test structures and circuits are proposed to address pre-bond TSV test accessibility issue and perform stuck-at-fault tests and TSV tests. By exploiting the inherent RC delay characteristics of TSV, a novel delay-based TSV test method is also proposed to map the variation of TSV-to-substrate resistance due to TSV defects to a test path delay change. Compared with state-of-art methods, the proposed BIST methodology addresses pre-bond TSV testing with a low-overhead integrated test solution which is compatible to existing 2D-IC testing method. The proposed BIST architecture and method can be implemented by standard DFT design flow and integrated into a unified pre-bond TSV test flow. Experiment results and robustness analysis are presented to verify the effectiveness of the proposed self-test methodology, architecture, and circuits.

Links to published journals:https://ieeexplore.ieee.org/document/6917214