A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile Robots

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First Author:J. Wang

Correspondence Author:C. Wang

Co-author:, Y. Zhan, Z. Wang, Z. Peng, J. Xu, B. Liu, G. Yu, F An, and X. Zou

Journal:IEEE Asian Solid State Circuit Conference (A-SSCC 2021)

Included Journals:EI

Document Type:C

DOI number:10.1109/A-SSCC53895.2021.9634793

Abstract:Matrix multiplication is an essential mathematical calculation in a wide range applications of signal processing, computer graphics and intelligent robots. The intelligent and autonomous robots involves various navigation algorithms (e.g. Extended Kalman Filter (EKF), reinforcement learning, A* and artificial potential field, etc.) [1] –[4] and deep neural network (DNN) algorithms (e.g. Darknet in YOLOv3), which all contain intensive matrix multiplications with different sizes and shapes. The emerging Intelligent and Autonomous Mobile Robots (I-AMRs) have put forward to a higher demand to efficient hardware acceleration of a comprehensive range of matrix multiplications as depicted in Fig. 1. Recent works have focused on the hardware acceleration of matrix multiplications optimized for a specified navigation or DNN algorithm [3] –[5], which cannot achieve high hardware utilization, high area and energy efficiency for the various matrix multiplications in I-AMRs.

Links to published journals:https://ieeexplore.ieee.org/document/9634793