An Energy-efficient Deep Belief Network Processor Based on Heterogeneous Multi-core Architecture with Transposable Memory and On-chip Learning

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Indexed by:Journal paper

First Author:J. Wu

Correspondence Author:C. Wang*

Co-author:, X. Huang, L. Yang, L. Wang, J. Wang, B. Liu, G. Yu, K. S. Chong,

Journal:IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)

Included Journals:SCI

Document Type:J

DOI number:10.1109/JETCAS.2021.3114396

Date of Publication:2021-09-27

Impact Factor:5.88

Abstract:With the growing interest of edge computing in the Internet of Things (IoT), Deep Neural Network (DNN) hardware processors/accelerators face challenges of low energy consumption, low latency, and data privacy issues. This paper proposes an energy-efficient processor design based on Deep Belief Network (DBN), which is one of the most suitable DNN models for on- chip learning. In this study, a thorough algorithm-architecture-circuit design optimization method is used for efficient design. The characteristics of data reuse and data sparsity in the DBN learning algorithm inspires this study to propose a heterogeneous multi-core architecture with local learning. In addition, novel circuits of transposable weight memory and sparse address generator are proposed to reduce weight memory access and exploit neuron state sparsity, respectively, for maximizing the energy efficiency. The DBN processor is implemented and thoroughly evaluated on Xilinx Zynq FPGA. Implementation results confirm that the proposed DBN processor has excellent energy efficiency of 45.0 pJ per neuron-weight update, which has been improved by 74% against the conventional design.

Links to published journals:https://ieeexplore.ieee.org/document/9548916