Indexed by: 会议

First Author: 王嘉慧

Correspondence Author: 缪向水

Co-author: Qu,L.W.,Chen,Y.,Long,X.M.,Zhang,L.,Sun,J.J.,Huang,D.Q.,童飞,Zhou,W.L.,周娇

Journal: Solid-State Electronics

Affiliation of Author(s): 华中科技大学

Discipline: Engineering

First-Level Discipline: Electronic Science And Technology

Document Type: C

Volume: 81

Page Number: 157-162

Key Words: High speed phase change memory Cell structure Super-lattice material Periphery circuit Testing

DOI number: 10.1016/j.sse.2012.12.011

Date of Publication: 4133-03-01

Abstract: A high SET/RESET speed phase change memory cell with a NMOS selector is achieved by optimizing cell structure, material, programming circuit and testing method. An asymmetric T-shape cell structure increases the current density in the programmable region and reduces thermal diffusion in the cell. Super-lattice phase change material has a lower thermal conductivity. The circuit has a fast response and reduces the falling time of RESET pulse to 0.9 ns which enables a fast phase change operation of the memory cell. The testing system has good signal integrity and transmits the undistorted ultrafast programming enable signal to I/O ports of the chip. The optimized SET time is 50 ns and RESET time is 2 ns.

Links to published journals: https://www.sciencedirect.com/science/article/pii/S0038110112003759?via%3Dihub