First Author: Chengyu Zhang,Yinghao Ma

Correspondence Author: Xingsheng Wang

Co-author: Yujie Song,Fan Yang,Yi Wang,Qiwen Wu,Xiangshui Miao

Journal: IEEE Transactions on Electron Devices

Included Journals: SCI、EI

Volume: 70

Issue: 12

Page Number: 6341-6346

Key Words: Logic-in-memory, memristor, multiplexer, V/R-R

DOI number: 10.1109/TED.2023.3327985

Date of Publication: 2023-11-04

Abstract: Instead of the von Neumann architecture, logic-in-memory (LIM) provides a revolutionary approach to promoting computing efficiency. Based on the earlier work of complete LIM 16 Boolean logics, this paper describes a memristor-based multiplexer (MUX) efficiently realized using a V/R-R logic method, despite the fact that MUX is one of complicated logics in the design of VLSI circuits. Following that, a unique 2-1 MUX is further created by merging destructive R-R logic with V/R-R logic, resulting in further device reduction. 2-1 MUX only requires 3~4 memristors and 4 steps. Furthermore, the technique can be implemented for a 4-1 MUX using 7 memristors and 10 steps. Tests and simulations validated their feasibility and correctness. The effect of resistor due to the flip voltage variation on the computation accuracy is further analyzed, and the cascaded serial scheme of the MUX is finally presented.

Links to published journals: https://ieeexplore.ieee.org/document/10305595