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第一作者：Q. Wang

通讯作者：G. Yu*

合写作者：Y. Zhan, B. Liu, J. Wu, Y. Shi, and C. Wang

发表刊物：IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2021)

收录刊物：EI

学科门类：工学

一级学科：电子科学与技术

文献类型：C

DOI码：10.1109/ICTA53157.2021.9661719

发表时间：2021-11-24

摘要：This paper proposes a reconfigurable hardware accelerator design of five major high-order operators for vision sensor based robot systems. These five high-order operators include convolution, median filtering, Euclidean distance, vector inner-product and iToF, which are intensively used in robot vision algorithms. In this work, a reconfigurable hardware accelerator design method for multiple high-order operators is proposed. FPGA implementation results show that the proposed design has achieved area efficiency with 17.54% reduced LUTs and 44.02% reduced FFs against the baseline hardware design of the five high-order operators. Case studies of Laplace edge-detection and iToF benchmark demonstrate the energy efficiency of proposed design with 19.70% and 6.2% reduction in energy consumption, respectively.