A High-Linearity, Energy-Efficient Switched-Capacitor Computing Circuit for Edge Applications

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First Author:Wenming Zhu

Correspondence Author:C. Wang*

Co-author:Huixuan Yin, Y. Zhao, G. Yu, Y. Yang, and

Journal:IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2023)

Included Journals:EI

Discipline:Engineering

First-Level Discipline:Electronic Science And Technology

Document Type:C

DOI number:10.1109/ICTA60488.2023.10364264

Date of Publication:2023-09-06

Abstract:This paper presents a passive switched-capacitor multiplication circuit for deep neural network computing in edge applications. A novel capacitor switching scheme is proposed to eliminate the computation error caused by non-binary-weighted parasitic capacitance, and dramatically increase the computing accuracy. It also simplifies the switching sequences to five phases to reduce the computation latency and improve the energy efficiency. Additionally, a mixed-signal multiply-add computing array is built with nine proposed switched-capacitor circuits and a SAR ADC. The simulation results in 28-nm technology show that the proposed array can achieve an energy efficiency of 11.94 TOPS/W and an average absolute computation error of 0.25 LSB, resulting in a classification accuracy of 98.43% when used for a 3-layer neural network on the MNIST dataset. As compared to the state-of-art mixed-signal computing circuit, the proposed circuit can enhance 1.19× energy efficiency and reduce 74% average absolute computation error.

Links to published journals:https://ieeexplore.ieee.org/document/10364264