An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity

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First Author:Jiajun Wu

Correspondence Author:C. Wang

Co-author:X. Huang, L. Yang, L. Wang, J. Wang, Z. Liu, K. S. Chong, S. W. Lin

Journal:IEEE Asian Solid State Circuit Conference (A-SSCC 2020)

Included Journals:EI

Document Type:C

DOI number:10.1109/A-SSCC48613.2020.9336135

Date of Publication:2020-11-09

Abstract:This paper proposes an energy-efficient multi-core processor design of restricted Boltzmann machine (RBM) with on-chip learning and reconfigurable sparsity. Inspired by bio-plausible variational probability flow (VPF) algorithm, our design significantly reduces the on-chip learning time and associated computation/energy as compared to conventional methods. The multi-core design with reconfigurable sparse weight connections further efficiently and flexibly reduces the required computation time and energy. FPGA implementation shows that the proposed design achieves 63.14 pJ per NW (neural weight) and 9.77 GNWs/s (neural weight update per second) at 128 MHz, which outperforms the baseline design by 44.0% and 24.3%, respectively.

Links to published journals:https://ieeexplore.ieee.org/document/9336135