An Energy-efficient SIFT based Feature Extraction Accelerator for High Frame-rate Video Applications

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Indexed by:Journal paper

First Author:B. Liu, Z. Yin,

Correspondence Author:C. Wang*

Co-author:X. Zhang, Y. Zhan, X. Hu, G. Yu, Y. Zheng,,and X. Zou

Journal:IEEE Trans. on Circuits and Systems-I Regular Papers (TCAS-I)

Included Journals:SCI

Discipline:Engineering

First-Level Discipline:Electronic Science And Technology

Document Type:J

DOI number:10.1109/TCSI.2022.3199475

Date of Publication:2022-08-25

Impact Factor:4.14

Abstract:Visual feature extraction is a key technology of computer vision for intelligent video processing. Efficient feature extraction is a fundamental problem in computer vision applications. Scale-Invariant Feature Transform (SIFT) is one of the most popular feature extraction algorithms because SIFT features are invariant to image scale and rotation and robust to changes in illumination and noise. However, SIFT is a computationally-intensive and power-hungry algorithm, which needs to be accelerated by efficient hardware design to achieve both high-speed feature extraction and high energy efficiency for many high frame-rate video applications at Artificial-intelligent Internet of Things edges. In this work, an energy-efficient SIFT based feature extraction accelerator is proposed. In the Gaussian pyramid and Differences of Gaussian (DoG) pyramid construction process, three design methods are proposed to reduce power consumption and improve information fidelity: a fast and slow dual clock domain design method with a reconfigurable design strategy is proposed to reduce the computation resources; a partial sum reuse design method is proposed to further reduce the computation resources and the amount of computation; a dynamic padding design method is proposed to solve the problem of information loss at image edges and corners after convolution operation. In the keypoint descriptor generation process, an optimized algorithm using circular region and polar coordinates is proposed to parallelize the main orientation assignment and descriptor generation to achieve high-speed processing, while maintaining a comparable matching accuracy with the state-of-the-art designs. The experiment results show that the proposed SIFT hardware accelerator is able to extract features by up to 162 frames per second (640×480 pixels) under 100 MHz, with the power consumption of 364.26 mW and energy efficiency of 2.25 mJ/frame based on 180 nm technology, which is suitable for many high frame-rate AIoT applications including autonomous driving cars and unmanned aerial vehicles.

Links to published journals:https://ieeexplore.ieee.org/document/9866790