Indexed by: Article

First Author: Zhouchao Gan

Correspondence Author: Xingsheng Wang

Co-author: Chenyu Zhang,Yinghao Ma,Dongdong Zhang,Xiangshui Miao

Journal: 8th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference

Included Journals: EI

Page Number: 1-3

DOI number: 10.1109/EDTM58488.2024.10511744

Date of Publication: 2024-03-06

Abstract: This paper presents a novel 2-1 multiplexer (MUX) scheme based on memristors that requires only 2 steps and 3 memristors. The proposed MUX logic can be executed natively in a memristor array, enabling the construction of complex logic and arithmetic functions. Its applications, including the 1-bit full adder (FA) and the 4-bit carry select adder (CSA), were further designed and experimentally verified. The experimental results illustrate the efficiency of the proposed MUX logic in accelerating the FA functions, which paves the way for building logic-in-memory systems.

Links to published journals: https://ieeexplore.ieee.org/document/10511744