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论文类型：期刊论文

第一作者：Tao Wu

通讯作者：Xingsheng Wang

合写作者： Haowen Luo, Xingsheng Wang,Asen Asenov, Xiangshui Miao

发表刊物：IEEE Transacations on Electron Devices

收录刊物：EI、SCI

所属单位：Huazhong University of Science and Technology

刊物所在地：USA

学科门类：工学

一级学科：电子科学与技术

文献类型：J

卷号：67

期号：6

页面范围：2255-2262

关键字：Compact model, FinFETs, parasitic resistance, scaling, TCAD

发表时间：2020-06-01

摘要：Due to the increasing importance and complexity of source/drain parasitic resistance (Rsd) in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware Rsd compact model is developed and comprehensively validated in respect of 7-nm bulk FinFET TCAD platform. Our TCAD model was calibrated againstGlobalFoundries/Samsung 7-nmFinFETtechnology experimental data and further validated by 2-D Poisson– Schrodinger simulation. Verilog-A coded SPICE Rsd compactmodel,coupledwithpropertransportmodels,indicates that the degradation of saturation current as well as the proportion of Rsd